[1] : The Free On-line Dictionary of Computing (27 SEP 03)

joint test action group
     
         jtag, or "ieee standard 1149.1" a
        standard specifying how to control and monitor the pins of
        compliant devices on a printed circuit board.
     
        each device has four jtag control lines.  there is a common
        reset trst and clock tclk.  the data line daisy chains
        one device's tdo pin to the tdi pin on the next device.
     
        the protocol contains commands to read and set the values of
        the pins and, optionally internal registers of devices.
        this is called "boundary scanning".  the protocol makes
        board testing easier as signals that are not visible at the
        board connector may be read and set.
     
        the protocol also allows the testing of equipment, connected
        to the jtag port, to identify components on the board by
        reading the device identification register and to control and
        monitor the device's outputs.
     
        jtag is not used during normal operation of a board.
     
        jtag technologies b.v. http://www.jtag.com/.
     
        boundary scan/jtag technical information - xilinx, inc.
        http://www.xilinx.com/support/techsup/journals/jtag/.
     
        java api for boundary scan faqs - xilinx inc.
        http://www.xilinx.com/products/software/sx/sxfaqs.htm.
     
        jtag boundary-scan test products - corelis, inc.
        http://www.corelis.com/products/scanovrv.html.
     
        "logic analyzers stamping out bugs at the cutting edge", edn
        access, 1997-04-10
        http://www.ednmag.com/ednmag/reg/1997/041097/08df_02.htm.
     
        ieee 1149.1 device architecture - boundary-scan tutorial from
        asset intertech, inc.
        http://www.asset-intertech.com/tutorial/arch.htm.
     
        "application-specific integrated circuits", michael john
        sebatian smith, published addison-wesley - design automation
        cafe
       
     http://www.dacafe.com/dacafe/edatools/edabooks/asic/book/ch14/ch14.2.htm.
     
        software debug options on asic cores - embedded systems
        programming archive http://embedded.com/97/feat9701.htm.
     
        designing for on-board programming using the ieee 1149.1
        jtag access port - intel
        http://developer.intel.com/design/flcomp/applnots/292186.htm.
     
        built-in self-test using boundary scan by texas instruments -
        edtn network
        http://www.edtn.com/scribe/reference/appnotes/md003e9a.htm.
     
        1999-11-15
     
     
see also:
standard printed circuit board daisy chains protocol internal registers boundary scanning 
lt;jtag technologies b.v.gt; lt;boundary scan/jtag technical information - xilinx, inc.gt; lt;java api for boundary scan faqs - xilinx inc.gt; lt;jtag boundary-scan test products - corelis, inc.gt; lt;"logic analyzers stamping out bugs at the cutting edge", edn access, 1997-04-10gt; lt;ieee 1149.1 device architecture - boundary-scan tutorial from asset intertech, inc.gt; lt;"application-specific integrated circuits", michael john sebatian smith, published addison-wesley - design automation cafegt; lt;software debug options on asic cores - embedded systems programming archivegt; lt;designing for on-board programming using the ieee 1149.1 jtag access port - intelgt; lt;built-in self-test using boundary scan by texas instruments - edtn networkgt; 

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