[1] : The Free On-line Dictionary of Computing (27 SEP 03)

microprocessor without interlocked pipeline stages
     
         mips a project at stanford university intended
        to simplify processor design by eliminating hardware
        interlocks between the five pipeline stages.  this means
        that only single execution cycle instructions can access the
        thirty two 32-bit general registers, so that the compiler
        can schedule them to avoid conflicts.  this also means that
        load/store and branch instructions have a one-cycle delay to
        account for.  however, because of the importance of multiply
        and divide instructions, a special hi/lo pair of
        multiply/divide registers exist which do have hardware
        interlocks, since these take several cycles to execute and
        complicate instruction scheduling.
     
        the project eventually lead to the commercial mips r2000
        processor.
     
        1995-02-09
     
     
see also:
stanford university interlock pipeline register compiler instruction scheduling 
mips r2000 

Microprocessor >> M Words
Microprocessor, definition of term: Microprocessor
microprocessor_pag1.html

Pipeline >> P Words
Pipeline, definition of term: Pipeline
pipeline_pag1.html

Without >> W Words
Without, definition of term: Without
without_pag1.html

Without Excepti >> W Words
Without Excepti, definition of term: Without Excepti
without+excepti_pag1.html

Pipeline Burst >> P Words
Pipeline Burst, definition of term: Pipeline Burst
pipeline+burst_pag1.html

To Do Without >> T Words
To Do Without, definition of term: To Do Without
to+do+without_pag1.html