[1] : The Free On-line Dictionary of Computing (27 SEP 03)

scalable processor architecture
     
         sparc an instruction set architecture designed
        by sun microsystems for their own use in 1985.  sun was a
        maker of 680x0-based unix workstations.  research
        versions of risc processors had promised a major step
        forward in speed but existing manufacturers were slow to
        introduce a risc type processor, so sun went ahead and
        developed its own, based on the university of california at
        berkley's risc i and risc ii 1980-2.  in keeping with
        their open philosophy, they licenced it to other companies,
        rather than manufacture it themselves.  the evolution and
        standardisation of sparc is now directed by the non-profit
        consortium sparc international, inc.
     
        sparc was not the first risc processor.  the amd 29000
        came before it, as did the mips r2000 based on stanford's
        design and hewlett-packard precision architecture cpu,
        among others.  the sparc design was radical at the time, even
        omitting multiple cycle multiply and divide instructions like
        a few others, while most risc cpus are more conventional.
     
        sparc implementations usually contain 128 or 144 registers,
        cisc designs typically had 16 or less.  at each time 32
        registers are available - 8 are global, the rest are allocated
        in a "window" from a stack of registers.  the window is moved
        16 registers down the stack during a function call, so that
        the upper and lower 8 registers are shared between functions,
        to pass and return values, and 8 are local.  the window is
        moved up on return, so registers are loaded or saved only at
        the top or bottom of the register stack.  this allows
        functions to be called in as little as 1 cycle.  like some
        other risc processors, reading global register zero always
        returns zero and writing it has no effect.  sparc is
        pipelined for performance, and like previous processors, a
        dedicated condition code register holds comparison results.
     
        sparc is "scalable" mainly because the register stack can be
        expanded up to 512, or 32 windows, to reduce loads and saves
        between functions, or scaled down to reduce interrupt or
        context switch time, when the entire register set has to be
        saved.  function calls are usually much more frequent, so the
        large register set is usually a plus.
     
        sparc is not a chip, but a specification, and so there are
        various implementations of it.  it has undergone revisions,
        and now has multiply and divide instructions.  most versions
        are 32 bits, but there are designs for 64-bit and
        superscalar versions.  sparc was submitted to the ieee
        society to be considered for the p1754 microprocessor
        standard.
     
        sparcr is a registered trademark of sparc international,
        inc. in the united states and other countries.
     
        the sparc architecture manual, v8, isbn 0-13-825001-4.
     
        1994-11-01
     
     
see also:
instruction set architecture sun microsystems 680x0 unix workstations risc 
university of california at berkley risc i risc ii sparc international, inc. amd 29000 
mips r2000 stanford hewlett-packard precision architecture cpu 
registers cisc pipelined condition code register interrupt 
context switch superscalar ieee p1754 

Scalable >> S Words
Scalable, definition of term: Scalable
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Processor >> P Words
Processor, definition of term: Processor
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Architecture >> A Words
Architecture, definition of term: Architecture
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Word Processor >> W Words
Word Processor, definition of term: Word Processor
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